VerilogEval v-2

'VerilogEval v-2' is a benchmark dataset used to evaluate the functional correctness and optimization capabilities of models in generating and refining Verilog code for hardware design tasks.

Papers using VerilogEval v-2 (7)

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation2025 · 2 citesInsights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback2025 · 1 citesExploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation2026SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation2026EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization2026CodeV-R1: Reasoning-Enhanced Verilog Generation2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation2025