VerilogEval-Machine

The 'VerilogEval-Machine' is a benchmark dataset used to evaluate the performance of automated Verilog code generation methods, specifically in the context of hardware design.

Papers using VerilogEval-Machine (5)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback2025 · 1 citesCraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair2024 · 2 citesEvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation2025RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution2023 · 9 cites