VerilogEval
Emerging21papers using it
2024first seen
VerilogEval is a benchmark dataset used to evaluate the effectiveness of Verilog generation methods by assessing their ability to produce correct, synthesizable, and timing-conscious RTL designs.
Papers using VerilogEval (21)
- RTL++: Graph-enhanced LLM for RTL Code GenerationRevisiting VerilogEval: A Year of Improvements in Large-Language Models
for Hardware Code GenerationVerilog-Evolve: Feedback-Driven and Skill-Evolving Verilog GenerationVeriContaminated: Assessing LLM-Driven Verilog Coding for Data ContaminationPyraNet: A Multi-Layered Hierarchical Dataset for VerilogLAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsignsMeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code GenerationEARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code GenerationDeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge BaseLLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language ModelsVeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft PromptsREvolution: An Evolutionary Framework for RTL Generation driven by Large Language ModelsUnderstanding and Mitigating Errors of LLM-Generated RTL CodeScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code GenerationVeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog GenerationAbstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware DesignVeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness ValidationRocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of ExpertsAutomatically Improving LLM-based Verilog Generation using EDA Tool
FeedbackHaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned
with HDL EngineersCodeV: Empowering LLMs for Verilog Generation through Multi-Level
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