VerilogEval

Papers using VerilogEval (21)

RTL++: Graph-enhanced LLM for RTL Code Generation2025 · 9 citesRevisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation2024 · 4 citesVerilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation2026VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination2025 · 1 citesPyraNet: A Multi-Layered Hierarchical Dataset for Verilog2024 · 1 citesLAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns2026MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation2026EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models2025Understanding and Mitigating Errors of LLM-Generated RTL Code2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation2025Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers2025Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback2024CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization2024