Verilog

The 'Verilog' dataset contains 20,392 high-quality samples of Verilog code used to evaluate and fine-tune Large Language Models (LLMs) for Register Transfer Level (RTL) code generation in hardware design automation.

Papers using Verilog (4)

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation2026VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation2025Benchmarking Large Language Models for Automated Verilog RTL Code Generation2022 · 10 citesA Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation2023 · 1 cites