RTLLM v-1.1

[!WARNING] Removed samplesWe have removed the samples asyn_fifo and multi_pipe_4bit due to incompatibilities with Verilator Take this into account! If you want the full dataset of 50 samples, go to the original repo. Disclaimer: I am not the original author and uploaded this here only for convenience, it only contains

Papers using RTLLM v-1.1 (3)

CodeV-R1: Reasoning-Enhanced Verilog Generation2025QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback2025