RTLLM

Papers using RTLLM (16)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination2025 · 1 citesCraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair2024 · 1 citesRTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning2026EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation2025LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models2025VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts2025REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models2025ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation2025Speculative Decoding for Verilog: Speed and Quality, All in One2025HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers2025AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs2024 · 19 citesRTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model2023 · 12 citesCoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation2024 · 3 citesLocation is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog2024 · 2 citesCodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization2024