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• AutoChip: Automating HDL Generation Using LLM Feedback
  2023 · 19 citations
• Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
  2023 · 14 citations
• Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
  2024 · 13 citations
• Benchmarking Large Language Models for Automated Verilog RTL Code Generation
  2022 · 11 citations
• VeriGen: A Large Language Model for Verilog Code Generation
  2023 · 10 citations
• Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
  2024 · 6 citations
• Evaluating LLMs for Hardware Design and Test
  2024 · 4 citations
• C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
  2024 · 1 citations
• Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
  2024 · 1 citations
• VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
  2026
• VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
  2025
• Model Cascading for Code: A Cascaded Black-Box Multi-Model Framework for Cost-Efficient Code Completion with Self-Testing
  2024