VerilogEval

Emerging

3papers using it

2025first seen

VerilogEval is a benchmark dataset used to evaluate the functional correctness of Register-Transfer Level (RTL) code generated from natural language specifications.

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Papers using VerilogEval (3)

Agentic Hardware Design as Repository-Level Code Evolution2026

Vflow: Discovering Optimal Agentic Workflows For Verilog Generation2025 · 1 cites

Chipcraftbrain: Validation-first RTL Generation Via Multi-agent Orchestration2026