Verilog-Eval

'Verilog-Eval' is a benchmark used to evaluate the performance of self-evolving agents in the context of hardware design by assessing their ability to manage and evolve Verilog code repositories.

Papers using Verilog-Eval (3)

Vflow: Discovering Optimal Agentic Workflows For Verilog Generation2025 · 1 citesChipcraftbrain: Validation-first RTL Generation Via Multi-agent Orchestration2026Agentic Hardware Design as Repository-Level Code Evolution2026