VerilogEval v-2

VerilogEval-v2-NTU This repository provides the patched version of VerilogEval-v2's dataset_spec-to-rtl, a benchmark designed to evaluate the capabilities of large language models in digital design and hardware description languages. The original VerilogEval-v2 dataset was developed by NVLabs and is available at https:

Papers using VerilogEval v-2 (2)

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback2025