VerilogEval

The 'VerilogEval' dataset is a benchmark that contains high-quality training samples for evaluating the performance of large language models in RTL (Register Transfer Level) code generation from functional descriptions.

Papers using VerilogEval (4)

LLM4RTL: Tool-Assisted LLM for RTL Generation2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation2026How LLMs Fail and Generalize in RTL Coding for Hardware Design?2026VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts2025