VerilogEval

The 'VerilogEval' dataset is a benchmark used to evaluate the performance of large language models in generating high-quality RTL (Register Transfer Level) code from functional descriptions.

Papers using VerilogEval (3)

LLM4RTL: Tool-Assisted LLM for RTL Generation2026Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation2026VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts2025